The present invention relates generally to the fabrication of electronic devices, such as integrated circuits in three dimensions. It relates in particular to a kit of compositions and a method of metallization of an insulating substrate having cavities such as through-silicon vias, by electroless deposition of a metallic layer of nickel or cobalt.
To produce integrated circuits in three dimensions (3D), the chips are superposed and connected together by vertical interconnections commonly called through-silicon vias (TSVs) filled with electrically-conducting copper.
The vias are generally etched in the silicon, then metallized to the desired depth before thinning the silicon wafer. During metallization, the vias are therefore closed or “blind” (and are called “blind vias”). The shape and size of the vias vary depending on their function and their position in the silicon wafer. They are generally characterized by their depth, their aperture diameter, and their aspect ratio, defining the ratio of depth to diameter of the via. For example, a cylindrical via of aspect ratio 10:1 has a diameter that is one tenth of its depth. The vias are generally of cylindrical shape, but there are also tapered vias whose opening is wider than the bottom. Structures having through-silicon vias are generally metallized by a process similar to the “damascene process” used in the field of microelectronics for making interconnecting elements, whose dimensions are smaller than those of the through-silicon vias. This process comprises a succession of steps including:                etching the vias in the silicon wafer;        depositing an insulating layer generally consisting of silicon oxide or of an insulating polymer;        depositing a barrier layer or “liner” for preventing migration of the copper;        filling the vias by electrodeposition of copper; and        removing the excess copper from the surface of the silicon wafer by mechanical-chemical polishing of the substrate surface.        
Before filling the vias with copper, it may be necessary to deposit a thin layer of metallic copper, called a seed layer, on the barrier layer; this lowers the electrical resistance of the surface of the barrier layer, and promotes uniform filling of the vias with copper.
The steps of depositing the barrier layer, of an optional seed layer, of filling with copper, and of polishing of the copper are commonly designated together with the expression “metallization of through-silicon vias”.
The insulating layer generally consists of a derivative of silicon such as silicon oxide or silicon nitride, or of an insulating polymer.
It is necessary to deposit a layer on the insulator, for preventing the migration of copper atoms under the effect of the electric current densities applied during operation of the integrated circuit. This layer, called “barrier to the diffusion of copper” or simply “barrier”, generally consists of tantalum (Ta), titanium (Ti), nickel (Ni), cobalt (Co), nickel-tungsten alloy (NiW), cobalt-tungsten alloy (CoW), nickel-boron alloy (NiB), cobalt-boron alloy (CoB), nickel-phosphorus alloy (NiP), cobalt-phosphorus alloy (CoP), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten alloy (TiW), tungsten carbon nitride (WCN) or of a combination of these materials.
The barrier layer is generally deposited in the vapor phase (PVD, CVD, ALD) but can also be formed from a metal salt solution, which deposits the metal on the surface of the insulating substrate.
When the substrate is an electrical conductor, electrodeposition of the metal on the surface of the substrate can be effected by polarizing the latter electrically. Electrodeposition is carried out for example by passing a current between the substrate to be coated, constituting a first electrode, and a second electrode placed in a bath containing the metal ions, and optionally various agents for improving the properties of the coating formed, such as the evenness, resistivity and fineness of the deposit.
The deposition of metal on the barrier layer can also be carried out by a non-electrochemical process, also called autocatalytic or “electroless”, which does not require electrical polarization of the substrate.
The invention finds application in particular in the deposition of a barrier layer based on nickel or cobalt in the course of a process for metallization of through-silicon vias. The substrate whose surface is to be coated is preferably a conducting or semiconducting substrate coated with an insulating layer having a collection of cavities notably intended to form through-silicon vias, such as those used for the fabrication of integrated circuits in three dimensions. The invention relates more particularly to a method of depositing a barrier layer based on nickel or cobalt, preferably in electroless conditions.
Electroless processes for depositing nickel-based barrier layers have already been described in the prior art.
Thus, patent application US 2005/0110149 describes a method of fabrication of a semiconductor device comprising an insulating intermediate layer based on silica covered with a monomolecular film of organic silane surface-modified with a compound containing palladium, the film thus modified being covered by an electroless process with a cobalt-based or nickel-based layer forming a barrier, on which a layer of copper can be deposited by electrodeposition.
A substantially similar method is described in patent application US 2008/0079154, which recommends, for improving the properties of adhesion between the different layers of the semiconductor device, carrying out two consecutive electroless treatments with a nickel-based compound (NiB), and then with a cobalt-based compound (CoWP).
Furthermore, repair of barrier layers based on titanium by electroless deposition of a thin layer of nickel and of boron has been suggested (FR 2 935713-A1).
Polyethylene-imines have already been used in electrodeposition solutions as copper complexing agents, notably for repairing copper seed layers, previously deposited on a barrier layer to copper diffusion (EP 1 479 793).
In document JP 2007-254 793, poly(allyl-amines) are proposed as nickel stabilizer in electroless processes, to prevent precipitation of reaction by-products on the nickel deposit.
The methods for deposition of barrier layers in the prior art, whether they are performed in the vapor phase, electrochemically or by an autocatalytic electroless reaction, make it possible to obtain a conformable barrier layer, i.e. matching, without discontinuity, the surface topography of the vias to be coated, and moreover for a wide range of aspect ratios. However, the bottom of the cavities is always less accessible to the deposition of material than the walls of the vias and the substrate surface, so that the thickness of the metallic barrier layer deposited at the bottom of the vias is always less than the thickness of the layer at the other levels of the deposit, whether on the walls of the via, at the opening of the via or on the substrate surface.
The nonuniform distribution of the deposit of the barrier layer on the surface of the cavities has essentially two drawbacks. Firstly, it makes subsequent filling of the vias with copper by electrodeposition more difficult. In fact, with smaller thickness of the metallic barrier layer, electrodeposition of copper on its surface in a subsequent step is more difficult, because of the lower current densities in the barrier layer resulting from the polarization of the substrate during the step of filling the vias with copper. Then, once the through-silicon vias are open through thinning of the silicon layer, the risks of electromigration of the copper atoms will be greater if the thickness of the barrier layer on the wall of vias is small, since the barrier function is less effective.